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<div class="header">
  <div class="headertitle"><div class="title">RTC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Real-Time Clock.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Real-Time Clock. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ad7e54d5c5a4b9fd1e26aca85b1e36c7f">&#9670;&#160;</a></span>ALRMAR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RTC_TypeDef::ALRMAR</td>
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<p>RTC alarm A register, Address offset: 0x1C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac5b2e3c0dcdcb569f3fe15dfe3794bc1">&#9670;&#160;</a></span>ALRMASSR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RTC_TypeDef::ALRMASSR</td>
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<p>RTC alarm A sub second register, Address offset: 0x44 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9816616e1f00955c8982469d0dd9c953">&#9670;&#160;</a></span>ALRMBR</h2>

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<p>RTC alarm B register, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a249009cd672e7bcd52df1a41de4619e1">&#9670;&#160;</a></span>ALRMBSSR</h2>

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<p>RTC alarm B sub second register, Address offset: 0x48 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab32c76ca1f3bd0f0f46d42c2dfa74524">&#9670;&#160;</a></span>BKP0R</h2>

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<p>RTC backup register 0, Address offset: 0x50 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5feba3d5adae3f234b3d172459163c5a">&#9670;&#160;</a></span>BKP10R</h2>

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<p>RTC backup register 10, Address offset: 0x78 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8fef38e1e122778601e18f5b757c037a">&#9670;&#160;</a></span>BKP11R</h2>

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<p>RTC backup register 11, Address offset: 0x7C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6606b5d249f923aa15ab74b382cbaf7e">&#9670;&#160;</a></span>BKP12R</h2>

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<p>RTC backup register 12, Address offset: 0x80 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a138903d4681455a660dccbaf3409263d">&#9670;&#160;</a></span>BKP13R</h2>

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<p>RTC backup register 13, Address offset: 0x84 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#adaae50f5c3213014fb9818eaee389676">&#9670;&#160;</a></span>BKP14R</h2>

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<p>RTC backup register 14, Address offset: 0x88 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a797f43f9cc1858baebd1799be288dff6">&#9670;&#160;</a></span>BKP15R</h2>

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<p>RTC backup register 15, Address offset: 0x8C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a181ad73082bde7d74010aac16bd373fc">&#9670;&#160;</a></span>BKP16R</h2>

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<p>RTC backup register 16, Address offset: 0x90 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a90a305a8e00b357f28daef5041e5a8b1">&#9670;&#160;</a></span>BKP17R</h2>

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<p>RTC backup register 17, Address offset: 0x94 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a171288f82cab2623832de779fb435d74">&#9670;&#160;</a></span>BKP18R</h2>

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<p>RTC backup register 18, Address offset: 0x98 </p>

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<p>RTC backup register 19, Address offset: 0x9C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5439bfca3708c6b8be6a74626f06111f">&#9670;&#160;</a></span>BKP1R</h2>

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<p>RTC backup register 1, Address offset: 0x54 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3e391ffa70a17dc5f95a841b5ec7554c">&#9670;&#160;</a></span>BKP20R</h2>

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<p>RTC backup register 20, Address offset: 0xA0 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a170847c24f166be0939a6eaeed7eeeee">&#9670;&#160;</a></span>BKP21R</h2>

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<p>RTC backup register 21, Address offset: 0xA4 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a679ec46535cae5149dc4d84e7c5d985c">&#9670;&#160;</a></span>BKP22R</h2>

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<p>RTC backup register 22, Address offset: 0xA8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7836b793c4ecc58a27733329f26550a7">&#9670;&#160;</a></span>BKP23R</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RTC_TypeDef::BKP23R</td>
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<p>RTC backup register 23, Address offset: 0xAC </p>

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<p>RTC backup register 24, Address offset: 0xB0 </p>

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<p>RTC backup register 25, Address offset: 0xB4 </p>

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<p>RTC backup register 26, Address offset: 0xB8 </p>

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<p>RTC backup register 27, Address offset: 0xBC </p>

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<p>RTC backup register 28, Address offset: 0xC0 </p>

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<p>RTC backup register 29, Address offset: 0xC4 </p>

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<p>RTC backup register 2, Address offset: 0x58 </p>

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<p>RTC backup register 30, Address offset: 0xC8 </p>

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<p>RTC backup register 31, Address offset: 0xCC </p>

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<p>RTC backup register 3, Address offset: 0x5C </p>

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<p>RTC backup register 4, Address offset: 0x60 </p>

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<p>RTC backup register 5, Address offset: 0x64 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a766e2071c5826e3a299ae1cd5bbf06f7">&#9670;&#160;</a></span>BKP6R</h2>

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<p>RTC backup register 6, Address offset: 0x68 </p>

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<p>RTC backup register 7, Address offset: 0x6C </p>

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<p>RTC backup register 8, Address offset: 0x70 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#abadf1ac26350bf00575428be6a05708b">&#9670;&#160;</a></span>BKP9R</h2>

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<p>RTC backup register 9, Address offset: 0x74 </p>

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<p>RTC calibration register, Address offset: 0x3C </p>

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<p>RTC control register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8750eae683cb3d382476dc7cdcd92b96">&#9670;&#160;</a></span>DR</h2>

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<p>RTC date register, Address offset: 0x04 </p>

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<p>RTC initialization and status register, Address offset: 0x0C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac4ec213226146fa48aa9b29e0e80b3ad">&#9670;&#160;</a></span>OR</h2>

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<p>RTC option register, Address offset: 0x4C </p>

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<p>RTC prescaler register, Address offset: 0x10 </p>

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<p>Reserved, Address offset: 0x18 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6082856c9191f5003b6163c0d3afcaff">&#9670;&#160;</a></span>SHIFTR</h2>

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<p>RTC shift control register, Address offset: 0x2C </p>

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<p>RTC sub second register, Address offset: 0x28 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a498ecce9715c916dd09134fddd0072c0">&#9670;&#160;</a></span>TAFCR</h2>

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<p>RTC tamper and alternate function configuration register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2e8783857f8644a4eb80ebc51e1cba42">&#9670;&#160;</a></span>TR</h2>

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<p>RTC time register, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa4633dbcdb5dd41a714020903fd67c82">&#9670;&#160;</a></span>TSDR</h2>

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<p>RTC time stamp date register, Address offset: 0x34 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1e8b4b987496ee1c0c6f16b0a94ea1a1">&#9670;&#160;</a></span>TSSSR</h2>

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<p>RTC time-stamp sub second register, Address offset: 0x38 </p>

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<p>RTC time stamp time register, Address offset: 0x30 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad54765af56784498a3ae08686b79a1ff">&#9670;&#160;</a></span>WPR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RTC_TypeDef::WPR</td>
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<p>RTC write protection register, Address offset: 0x24 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad93017bb0a778a2aad9cd71211fc770a">&#9670;&#160;</a></span>WUTR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RTC_TypeDef::WUTR</td>
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<p>RTC wakeup timer register, Address offset: 0x14 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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